Programme

Sunday, July 23rd, 2017

15:00 - 17:00 Informal meeting of the IEEE 754 Floating-Point Standards committee

Room 508, EEE building, building 16

Monday, July 24th, 2017

08:30 - 09:00 Registration / Breakfast

09:00 - 09:10 Welcome and Introduction

09:10 - 10:10 Session 1 : Keynote Talk

The Rise of Multiprecision Arithmetic Prof. N. Higham, Manchester University

10:10 - 10:40 Coffee break

10:40 - 12:20 Session 2 : Multiprecision Arithmetic

Multiple precision floating point arithmetic on SIMD processors
J. van der Hoeven (LIX, Palaiseau, France)

Multiprecision Multiplication on ARMv8
Z. Liu (University of Waterloo, Canada), K. Järvinen (University of Helsinki, Finland), W. Liu (Nanjing University, China), and H. Seo (I2R, Singapore)

Optimized Binary64 and Binary128 Arithmetic with GNU MPFR
V. Lefèvre and P. Zimmermann (LORIA, Nancy, France)

Implementation and performance evaluation of an extended precision floating-point arithmetic library for high-accuracy semi-definite programming
M. Joldes (LAAS, Toulouse, France), and J-M. Muller and V. Popescu (LIP, Lyon, France)

12:20 - 13:35 Lunch

13:35 - 14:50 Session 3 : Arithmetic Operators

Normalizing or Not Normalizing? An Open Question for Floating-Point Arithmetic in Embedded Systems
S. Gonzalez-Navarro and J. Hormigo (Universidad de Málaga, Spain)

On Lifting-Based Fixed-Point Complex Multiplications and Rotations
O. Gustafsson (Linköping University, Sweden)

A Number System Approach for Adder Topologies
A. Vazquez and E. Antelo (University of Santiago de Compostela, Spain)

14:50 - 15:20 Coffee Break

15:20 - 15:50 Session 4 : Invited Talk

Arb: Efficient Arbitrary-Precision Midpoint-Radius Interval Arithmetic
F. Johansson (IMB, Bordeaux, France)

15:50 - 17:40 Session 5 : Realizing Efficient Matrix Computations (special session)

QRD for Parallel Arithmetic Structures
M. Langhammer (Intel, UK)

Optimizing Matrix Multiplication on Intel Xeon PhiTM x200 Architecture
M. E. Guney, K. Goto, T. B. Costa, S. Knepper, L. Huot, A. A. Mitranok, and S. Story (Intel, USA)

Accelerating Matrix Processing with GPUs
N. Malaya, S. Che, J. L. Greathouse, R. van Oostrum, and M. J. Schulte (AMD, USA)

Algorithms and Arithmetic: Choose Wisely
G.A. Constantinides (Imperial College, London)

20:00 - 22:00 Conference Drinks reception at the Science Museum

Tuesday, July 25th, 2017

08:30 - 09:00 Breakfast

09:00 - 10:40 Session 6 : Floating-Point Error Analysis

The classical relative error bounds for computing \(\sqrt{a^2 + b^2}\) and \(c/\sqrt{a^2 + b^2}\) in binary floating-point arithmetic are asymptotically optimal
C.-P. Jeannerod, J-M. Muller, and A. Plet (LIP, Lyon, France)

Certified Roundoff Error Bounds using Bernstein Expansions and Sparse Krivine-Stengle Representations
A. Rocca, T. Dang, and V. Magron (Verimag, France)

Round-off Error Analysis of Explicit One-Step Numerical Integration Methods
S. Boldo and F. Faissole (LRI, Orsay, France), and A. Chapoutot (ENSTA ParisTech, France)

ULPs and Relative Error
M. Cornea (Intel, USA)

10:40 - 11:10 Coffee Break

11:10 - 12:35 Session 7 : Hardware for Fast and Reproducible Arithmetic

High-Precision Anchored Accumulators for Reproducible FP Summation
D.R. Lutz and C.N. Hinds (ARM, USA)

Modified FMA for exact low precision product accumulation
N. Brunie (kalray, France)

A Hardware Accelerator for Computing an Exact Dot Product
J. Koenig, D. Biancolin, J. Bachrach, and K. Asanovic (UC Berkeley, USA)

12:35 - 13:50 Lunch

13:50 - 14:40 Session 8 : Keynote Talk

Large scale numerical simulations of the climate J-C. Rioual, Met Office

14:40 - 15:30 Session 9 : Arithmetic in FPGAs

Flexible fixed-point function generation for FPGAs
B. Pasca (Intel, France) and M. Istoan (INSA, Lyon, France)

Optimal Design of Large Multipliers for FPGAs
M. Kumm, J. Kappauf and P. Zipf (University of Kassel, Germany), and M. Istoan (INSA, Lyon, France)

15:30 - 16:00 Coffee break

16:00 - 17:55 Session 10 : Arithmetic in DSP (Special Session)

Optimal Streamed Linear Permutations
F. Serre and M. Püschel (ETH Zurich, Switzerland)

On improving the performance per area of ASTC with a multi-output decoder
K.C. Rovers and S. Elliott (Imagination Technologies, UK)

Approximate Neumann Series or Exact Matrix Inversion for Massive MIMO
O. Gustafsson, E. Bertilsson, J. Klasson, and C. Ingemarsson (Linköping University, Sweden) et al

Floating Point Tangent Implementation for FPGAs
M. Langhammer (Intel, UK) and B. Pasca (Intel, France)

High performance and energy efficient circuit technologies for machine learning accelerators in sub-10nm process generations
R. Krishnamurthy (Intel, USA)

19:00 - 22:00 Conference banquet at Ognisko

Wednesday, July 26th, 2017

08:30 - 09:00 Breakfast

09:00 - 10:15 Session 11 : Cryptography

Fast Arithmetic Modulo \( 2^x p^y \pm 1 \)
J. Bos and S. Friedberger (NXP, Belgium)

Efficient Leak Resistant Modular Exponentiation in RNS
A. Lesavourey and C. Negre (LIRMM, France), and T. Plantard (University of Wollongong, Australia)

A New Multiplicative Inverse Architecture in Normal Basis Using Novel Concurrent Serial Squaring and Multiplication
A. Monfared, H. El-Razouk, and A. Reyhani-Masoleh (Western University, Canada)

10:15 - 10:45 Coffee break

10:45 - 12:00 Session 12 - Miscellaneous Topics in Computer Arithmetic

A Sum Error Detection Scheme for Decimal Arithmetic
A. Vazquez and E. Antelo (University of Santiago de Compostela, Spain)

Reliable verification of digital implemented filters against frequency specifications
A. Volkova, C. Lauter, and T. Hilaire (Sorbonne University, France)

A Parallel Method for the Computation of Matrix Exponential based on Truncated Neumann Series
V.S. Dimitrov, D.F.G. Coelho and L. Rakai (University of Calgary, Canada), V. Ariyarathna and A. Madanayake (University of Akron, USA), and R.J. Cintra (Universidade Federal de Pernambuco, Brazil)

12:00 - 12:10 Conference close

12:30 - 17:30 (Optional) Post-conference trip to Bletchley Park